SiO₂/Gd₂O₃/GaN METAL OXIDE SEMICONDUCTOR

FIELD EFFECT TRANSISTORS

J.W. Johnson¹, B.P. Gila², B. Luo¹, K.P. Lee², C.R. Abernathy², S.J. Pearton²,

J.I. Chyi³, T.E. Nee³, C.M. Lee³, C.C. Chuo³, and F. Ren¹

1. Department of Chemical Engineering, University of Florida, Gainesville, FL 32611

2. Department of Materials Science and Engineering, University of Florida, Gainesville, FL 32611

3. Department of Electrical Engineering, National Central University, Chung-Li, 32054, Taiwan

ABSTRACT

GaN based metal oxide semiconductor field effect transistors were demonstrated using a stacked gate oxide consisting of single crystal Gd₂O₃ and amorphous SiO₂. Gd₂O₃ provides a good oxide/semiconductor interface and SiO₂ reduces the gate leakage current and enhances oxide breakdown voltage. Charge modulation of the n-channel depletion mode MOSFET was achieved for gate voltage from +2 to -4V. The source-drain breakdown voltage exceeded 80V. An intrinsic transconductance of 61 mS/mm was obtained at a gate-source and drain-source bias of -0.5V and 20V, respectively. This is the first demonstration of epitaxial Gd₂O₃ growth on GaN and the first use of Gd₂O₃ as an insulating layer for nitride electronic device applications.

INTRODUCTION

Advances in material quality and device processing have led to promising results for III-nitride electronic devices for high temperature and high power applications. [1,2] GaN metal semiconductor field effect transistors (MESFETs) and GaN/AlGaN heterostructure field effect transistors (HFETs) exhibiting excellent device characteristics have been reported by numerous groups. [3-13] However, leakage from the Schottky gate of such devices is a major concern for operation at elevated temperatures. An attractive alternative to GaN MESFETs and HFETs is the use of an insulated gate metal oxide semiconductor (MOS) structure, reducing gate leakage and power consumption. Unfortunately, the availability of a thermally stable gate dielectric with sufficiently low density of interface states (D_it) has been a historically troublesome issue for III-V materials.

Recently Ga₂O₃(Gd₂O₃) evaporated from a single crystal Ga₅Gd₃O₁₂ source has been shown to effectively passivate GaAs and InGaAs, and both n-and p-type enhancement mode MOSFETs were demonstrated. [14,15] A similar approach was used to fabricate Ga₂O₃(Gd₂O₃)/GaN MOS diodes with low D_it and led to the demonstration of the first GaN MOSFET. [16] This device exhibited significantly lower leakage current relative to a conventional GaN MESFET. However, compositional control of the (Ga₂O₃)_x(Gd₂O₃)_y is difficult due to its strong dependence on substrate temperature during oxide growth. An alternative is the use of single crystal Gd₂O₃, which has been demonstrated on GaAs by electron beam deposition from a Gd₂O₃ source. [17,18] The material properties of Gd₂O₃ also make it an attractive candidate for use as a gate insulator on GaN, as summarized in Table I. [19-21] In addition to the large bandgap and dielectric constant and high melting temperature, Gd₂O₃ is expected to show increased compositional uniformity in the growth direction relative to Ga₂O₃(Gd₂O₃). [22] In addition, Gd₂O₃ exhibits similar atomic symmetry in the (111) plane as the GaN (0001) basal plane, suggesting the potential for growth of an epitaxial dielectric.

In this study, we describe the device fabrication and DC characteristics of an n-channel depletion mode GaN MOSFET using a stacked gate dielectric of SiO₂/Gd₂O₃. This is the first report of single crystal Gd₂O₃ on GaN and the first demonstration of a GaN MOSFET using Gd₂O₃ in the gate insulator.

EXPERIMENTAL

The nitride layer structure consisted of 2mm unintentionally doped GaN and a 700Å Si-doped GaN channel grown by MOCVD on a c-Al₂O₃ substrate. Hall measurement indicated a channel doping level in the low-10¹⁸ cm^-3. The wafer was prepared for oxide growth by a 3 min. dilute HCl dip, 25 min. UV-ozone exposure, and 5 min. dilute HF dip. The Gd₂O₃ was grown in a Riber 2300 gas-source molecular beam epitaxy (GSMBE) system equipped with a Wavemat MPDR 610 electron cyclotron resonance (ECR) plasma source. After loading, the wafer was heated to 700°C to desorb the native oxides, then cooled to the growth temperature of 650°C. Growth proceeded at 1´10^-4 torr oxygen pressure in the ECR plasma head at 200W forward power, with a Gd cell temperature of 1230°C. X-ray diffraction showed a single crystalline Gd₂O₃ structure for the 700Å film. Further details of the oxide growth will be presented elsewhere. [23]

A schematic of the processing sequence and final device structure of the planar n-channel depletion mode GaN MOSFET is given in Figure 1. Device fabrication began with a wet etch of Gd₂O₃ to open source and drain ohmic contact windows using HCl as the etchant and photoresist AZ-1818 as the mask. Ti(200Å)/Al(600Å)/Au(1000Å) ohmic contacts were deposited by electron-beam evaporation. Oxygen implantation was used for device isolation. A similar O⁺ implantation scheme has previously been shown to yield sheet resistance in GaN on the order of 10¹² W/o. [24] To enhance the gate breakdown voltage, a 300Å layer of SiO₂ was electron-beam evaporated onto the Gd₂O₃ surface in the photolithographically-defined gate contact region. This was followed under vacuum by evaporation of Ti(100Å)/Au(1000Å) Schottky contacts to the SiO₂ surface.

RESULTS AND DISCUSSION

When deposited under optimum conditions, Gd₂O₃ was grown epitaxially on GaN, as verified by reflection high energy electron diffraction (RHEED) and cross-sectional transmission electron microscopy (XTEM). An XTEM micrograph of the Gd₂O₃/GaN interface is shown in Figure 2. From this image, the interface is seen to be

quite smooth despite a somewhat rough nitride surface. However, there is still a relatively large difference in lattice spacing between Gd₂O₃ and GaN, which contributed to a high number of dislocations in the oxide film. These dislocations act as current leakage paths and caused the breakdown voltage of the as-grown Gd₂O₃ to be rather low. In order to improve the breakdown for device fabrication, amorphous SiO₂ was deposited on the Gd₂O₃ surface. The formation of a stacked gate dielectric of SiO₂/Gd₂O₃ allowed the interfacial properties of Gd₂O₃/GaN to be maintained, while reducing leakage by terminating the dislocations in the crystalline oxide. Figure 3 illustrates the significant reduction in gate leakage after SiO₂ deposition. The breakdown field of the insulator improved from 0.3 to 0.8 MV/cm. Gate reverse leakage current density was 5´10^-6 A/cm² at a gate-source bias (V_GS) of -10V and remained below 10 nA at V_GS = -70V for the 1´200 mm² device, clearly demonstrating the benefit of the insulated gate MOS structure.

Capacitance-voltage data were measured at room temperature using a HP4284 LCR meter. Figure 4 illustrates C-V characteristics of a fat FET with a gate dimension of 36´100mm², measured in the dark at a sweep rate of 100mV/sec. and frequencies from 1kHz to 1MHz. Charge modulation from accumulation to depletion is observed. The absence of surface inversion is due to the wide band gap and correspondingly low room temperature minority carrier generation rate of GaN, consistent with previous reports on wide bandgap MIS structures. [25,26] Both the forward and reverse sweep data are included in Fig. 3 for the SiO₂/Gd₂O₃/GaN structures, and a slight capacitance hysteresis is observed. However, Figure 5 shows a 100 kHz C-V trace for a 400 mm diameter Gd₂O₃/GaN diode illustrating negligible hysteresis, suggesting that the hysteresis in Fig. 4 may be related to the SiO₂, not Gd₂O₃. More work is needed to characterize the interfacial and bulk electrical properties of these Gd₂O₃/GaN structures. From a plot of 1/C² vs. V for the long-gate MOSFET, the doping profile of the GaN layer structure was calculated and is plotted in Fig. 6 versus applied gate bias. The doping concentration in the channel is ~3´10¹⁸ cm^-3, consistent with Hall measurements, and the carrier concentration in the bulk UID GaN is ~8´10¹⁵ cm^-3.

Drain I-V characteristics of a 1´200 mm² gate dimension SiO₂/Gd₂O₃/GaN MOSFET were mesured with an HP4145A and are shown in Fig. 7. The drain-source breakdown exceeds 80V. For these high breakdown devices, charge modulation could be demonstrated for gate voltages from +2 to -5V. Other depletion mode devices of identical geometry could be modulated at an accumulation bias of +7V, verifying the high quality of the Gd₂O₃/GaN interface. A maximum intrinsic transconductance of 61 mS/mm was measured at V_GS=-0.5V and V_DS=20V. The high output conductance of the drain IV in Fig. 6 may have been caused by short channel effects due to the high-10¹⁵ cm^-3 doping in the buffer layer. The device had high knee voltage and parasitic resistance because the ohmic contact was annealed only to ~300ºC. Although the O⁺ isolation implant provided a good sheet resistivity for the as-implanted sample, the thermal stability of the implanted samples was quite poor. [24] After annealing the sample at 400°C for 1 min., the sheet resistivity can decrease by more than an order of magnitude. To optimize the ohmic contact annealing and device isolation processes, Cr⁺ and Fe⁺ implantation may be needed. Both of them showed good thermal stability up to 600°C. [27]

In summary, we have successfully grown single crystal Gd₂O₃ on GaN by GS-MBE and fabricated n-channel depletion mode GaN MOSFETs with a stacked SiO₂/Gd₂O₃ gate insulator. Devices showed high drain breakdown voltage, low gate leakage, and excellent charge modulation.

ACKNOWLEDGEMENTS

The authors gratefully acknowledge the U.S. Office of Naval Research under Contract No. N00014-98-1-02-04 (J.C. Zolper), and DARPA/EPRI under contract MDA972-98-1-0006-0204 (D. Ritter/B. Damsky) for support of this work.

REFERENCES

[1] S.J. Pearton, J.C. Zolper, R.J. Shul, and F. Ren, J. Appl. Phys., 86, 1 (1999).

[2] S.C. Jain, M. Wilander, J. Narayan, and R. Van Overstaeten, J. Appl. Phys., 87, 965 (2000).

[3] P.M. Asbeck, E.T. Yu, S.S. Lau, G.J. Sullivan, J. Van Hove and, J.M. Redwing, Electron. Lett., 33, 1230 (1997).

[4] S.C. Binari, W. Kruppe, H.B. Dietrich, G. Kelner, A.E. Wickenden, and J.A. Freitas, Solid State Electron., 41, 1549 (1997).

[5] J. Burm, K. Chu, W.J. Schaff, L.F. Eastman, M.A. Khan, Q. Chen, J.W. Yang, and M.S. Shur, IEEE Electron. Dev. Lett., 18, 141 (1997).

[6] R. Gaska, Q. Chen, J. Yang, A. Osinsky, M.A. Khan, and M.S. Shur, IEEE Electron. Dev. Lett., 18, 492 (1997).

[7] G.J. Sullivan, M.Y. Chen, J.A. Higgins, J.W. Yang, Q. Chen, R.C. Pierson and B.T. McDermott, IEEE Electron. Dev. Lett., 19, 198 (1998).

[8] A.T. Ping, Q. Chen, J.W. Yang, M.A. Khan and I. Adesida, IEEE Electron. Dev. Lett., 19, 54 (1998).

[9] O. Akatas, Z.F. Fan, A. Botcharev, S.N. Mohammad, M. Roth, T. Jenkins, L. Kehias and H. Morkoc, IEEE Electron. Dev. Lett., 18, 293 (1997).

[10] R.J. Trew, M.W. Shin, and V. Gatto, Solid-State Electron., 41, 1561 (1997).

[11] Y.F. Wu, B.P. Keller, S. Keller, J.J. Xu, B.J. Thibeault, S.P. Denbaars, U.K. Mishra, IEICE Trans. on Electronics, 11, 1895 (1999).

[12] Q. Chen, J.W. Yang, M. Blasingame, C. Faber, A.T. Ping, and I. Adesida, Mat. Sci. and Eng. B, 59, 395 (1999).

[13] D.E. Grider, N.X. Nguyen, and C. Nguyen, Solid-State Electron., 43, 1473 (1999).

[14] F. Ren, M. Hong, J.M. Kuo, W.S. Hobson, J.R. Lothian, H.S. Tsai, J. Lin, J.P. Mannaerts, J. Kwo, S.N.G. Chu, Y.K. Chen, and A.Y. Cho, 1997 IEEE GaAs IC Symposium, Anaheim, CA Oct. 12-15, 1997.

[15] F. Ren, J.M. Kuo, M. Hong, W.S. Hobson, J.R. Lothian, J. Lin, H.S. Tsai, J.P. Mannaerts, J. Kwo, S.N.G. Chu, Y.K. Chen, and A.Y. Cho, IEEE Electron. Dev. Lett., 19, 309 (1997).

[16] F. Ren, M. Hong, S.N.G. Chu, M.A. Marcus, M.J. Schurman, A. Baca, S.J. Pearton, and C.R. Abernathy, Appl. Phys. Lett., 73, 3893 (1998).

[17] M. Hong, Y. C. Wang, F. Ren, J. P. Mannaerts, J. Kwo, A. R. Kortan, J. N. Baillargeon, and A. Y. Cho, 2000 Electrochemical Soc. Toronto, Canada Meeting Proceedings Vol. PV2000-1, p. 292.

[18] M. Hong, J. Kwo, A.R. Kortan, J.P. Mannaerts, A.M. Sergent, Science, 283, 1897 (1999).

[19] S.S. Derbeneva, S.S. Batsano, Dokl. Chem., 175, 710 (1967).

[20] S.S. Batsono, E.V. Dulepov, Soviet Physics – Solid State, 7(4), 995 (1965).

[21] K.A. Gschneider, Rare Earth Alloys [Russian translation], Izd. Mir., (1965).

[22] B.P. Gila, K.N. Lee, J. Laroche, F. Ren, S.M. Donovan, C.R. Abernathy, and J. Han, Mat. Res. Soc. Spring 1999 Meeting, San Francisco, CA, April 5-9, 1999.

[23] B.P. Gila, W. Krishnamoorthy, W. Johnson, C.R. Abernathy, F. Ren, and S.J. Pearton, to be presented at the 47^th Int. Symp. of the AVS, Boston, MA, October 2-6, 2000.

[24] G. Dang, X.A. Cao, F. Ren, S.J. Pearton, J. Han, A.G. Baca, and R.J. Shul, J. Vac. Sci. and Tech. 17, 2015 (1999).

[25] Y. Wang, J.A. Cooper, Jr., M.R. Melloch. S.T. Aheppard, J.W. Palmour, and L.A. Lipkin, J. Electron. Mater., 25, 899 (1996).

[26] T. Hashizume, E. Alekseev, D. Pavlidis, K.S. Boutros, and J.M. Redwing, J. Appl. Phys., 88, 1983 (2000).

[27] X. A. Cao, S. J. Pearton, and F. Ren, Crit. Rev. in Solid State & Mat. Sci., (to be published).

Figure and Table Captions

Table I. Material properties of GaN and of candidate dielectrics for GaN-based electronic devices.

Figure 1. Processing sequence for GaN MOSFET. a.) wafer structure, b.) Gd₂O₃ etch, c.) ohmic metallization, d.) isolation implant, e.) post-implant structure showing isolation of discrete devices, f.) SiO₂ and gate contact metallization; final device structure.

Figure 2. High resolution XTEM of Gd₂O₃ / GaN interface.

Figure 3. Forward and reverse gate leakage current before and after SiO₂ deposition.

Figure 4. Forward- and reverse-sweep C-V characteristics of a 36 ´100mm² SiO₂/Gd₂O₃ FET.

Figure 5. 100 kHz C-V sweep of 400mm Gd₂O₃/GaN diode exhibiting negligible capacitance hysteresis.

Figure 6. Doping density of nitride layer structure calculated from C-V measurements.

Figure 7. DC output characteristics of 1´200mm² gate dimension GaN MOSFET.

	GaN	SiO2	Si3N2	AlN	Ga2O3	Ga2O3/ (Gd2O3)	Gd2O3
Structure	2H	Amor.	Amor.	2H	Hex./ Mono.	Amor.	Bixbyite
Mismatch to GaN (%)	-	-	-	2.5	56	-	20
Bandgap (eV)	3.39	9.0	5.0	6.2	4.4	4.7	5.3
Static Dielectric Constant, e	8.9	3.9	5.0	8.5	10	10-11.4	11.4
TMP (K)	>2500	1993	2173	3073	2013	-	2670